Developers report that porting a custom YOLOv5 model to the takes less than two hours from Python script to running on the evaluation board. This low friction is deliberately designed to capture the maker and startup market, historically underserved by enterprise-focused AI chips.
As of Q2 2026, the is available in several form factors: UZU-013-AI
The chip integrates 128 ASTC cores, 4 RISC-V management cores, and a dedicated 8MB SRAM cache arranged in a hierarchical mesh. This allows the UZU-013-AI to partition workloads intelligently: the RISC-V cores handle control flow and pre/post-processing, while the ASTCs focus exclusively on tensor operations. Developers report that porting a custom YOLOv5 model
Searching through technology databases and AI research repositories like IASP and developer platforms like Bubble does not yield any results for this specific designation. It is possible this term refers to: 4 RISC-V management cores